Samsung's hybrid bonding technology is expected to be used in NVIDIA's next-generation AI accelerator Feynman, with the chip featuring custom HBM.

Samsung Electronics has begun constructing a Die-to-Wafer (D2W) hybrid bonding production line at its Pyeongtaek P5 plant, targeting advanced packaging for next-generation HBM and logic semiconductors. Dutch firm Besi is the preferred core equipment supplier, with Samsung planning to procure around 50 hybrid bonding machines—each priced at approximately 6 billion won (about $4.3 million), twice the cost of competing products. However, negotiations have moved slowly due to Samsung’s demand for custom modifications to the equipment architecture, and Besi, which also supplies TSMC and Micron, is cautious about modifying machines exclusively for Samsung. Samsung is also considering local alternatives: its subsidiary SEMES has completed development of D2W hybrid bonding machines and delivered samples for validation earlier this year; Hanwha Semitech finished developing its second-generation "SHB2 Nano" in February, and sent samples to SK Hynix in April. Its cluster system integrating EFEM, plasma activation, and cleaning modules gives it a differentiated competitive edge. This technology uses hybrid copper bonding to replace traditional thermocompression bonding, enabling direct bonding of copper and dielectric materials and drastically shortening interconnect lengths. Its core application is custom HBM: vertically stacking HBM DRAM layers directly on logic dies that include customers’ computing circuits and IP to form 3D system-in-package (SiP). Citrini analyst Jukan noted that hybrid bonding is expected to be used in NVIDIA’s next-generation AI accelerator Feynman, which will adopt custom HBM, and the technology’s rollout timeline "has been pushed back from HBM4E". Samsung’s internal projections indicate large-scale application will not be realized until around 2029-2030, a timeline that aligns with NVIDIA’s expected window for Feynman.