Samsung Explores New Memory Tech: Vertically Stacked on AI Accelerators, 10x Denser Than Traditional HBM5

Samsung Electronics unveiled its V10 Bonding V-NAND, also known as BV-NAND, prototype at the Future Memory and Storage (FMS) Conference held in Santa Clara, California. The chip features over 400 layers and adopts a new wafer bonding architecture to boost storage density and enhance performance. Samsung stated that its BV-NAND technology delivers around 58% higher storage density than the previous-generation V9 NAND, while improving read, write, and input/output performance to meet the growing demand from AI systems for higher-capacity, more energy-efficient storage solutions. Samsung also demonstrated what it claims are the industry’s first conceptual models of zHBM and zNAND-O architectures. This technology stores more data in a smaller space by vertically stacking memory cells. Unlike traditional HBM, which is packaged side-by-side with AI processors, Samsung’s zHBM vertically stacks memory on top of AI accelerators to shorten data transmission distances, boost bandwidth, and improve energy efficiency. Samsung noted that its wafer bonding technology is expected to achieve over 10 times the storage density of conventional HBM5 memory, while tripling energy efficiency and cutting thermal resistance by more than half.