Solv Protocol: BTC+ smart contract attacked due to deployer’s private key leak, subscriptions and redemptions expected to resume within two weeks.

Samsung Electronics has commenced construction of a Die-to-Wafer (D2W) hybrid bonding production line at its P5 plant in Pyeongtaek, targeting advanced packaging for next-generation High Bandwidth Memory (HBM) and logic semiconductors. Samsung’s top pick for core equipment suppliers is Dutch firm Besi; the company plans to procure around 50 hybrid bonding machines, each priced at roughly 6 billion won (about $4.3 million) — twice the cost of competing products. However, negotiations have moved slowly due to Samsung’s demand for custom modifications to the machine architecture, and Besi, which also supplies TSMC and Micron, is cautious about modifying equipment exclusively for Samsung. Samsung is simultaneously evaluating local alternatives: its subsidiary SEMES has completed development of D2W hybrid bonding machines and delivered samples for validation earlier this year. Hanwha Semitech finished developing its second-generation "SHB2 Nano" in February, and sent samples to SK Hynix in April. Its cluster system integrating Equipment Front End Module (EFEM), plasma activation, and cleaning modules offers distinct competitive advantages. This technology replaces traditional thermocompression bonding with hybrid copper bonding, enabling direct bonding of copper and dielectric materials and drastically shortening interconnect lengths. Its core application is custom HBM: vertically stacking HBM DRAM layers directly on logic dies containing customers’ computing circuits and intellectual property (IP) to form 3D system-in-package (SiP) solutions. Citrini analyst Jukan stated that hybrid bonding is expected to be used in NVIDIA’s next-generation AI accelerator Feynman, which will adopt custom HBM, with the technology’s deployment timeline "pushed back from HBM4E". Samsung’s internal projections indicate large-scale commercialization will not be achieved until around 2029–2030, a timeline that aligns with NVIDIA’s expected window for Feynman.

According to the Financial Times, US President Donald Trump will impose new tariffs on dozens of countries as early as this week.

High-tech industry research firm TrendForce points out that while servers account for over 40% of total NAND flash demand, smartphones and laptops combined still make up nearly 40%, continuing to significantly impact overall demand. On the inventory front, memory manufacturers’ stock levels remain relatively low. Though module manufacturers’ inventories have risen due to weak consumer market conditions, inventories held by other buyers stay controllable. Taking all these factors into account, TrendForce projects the NAND flash bit supply-demand gap will hold at 4%–5% in 2026, signaling ongoing supply shortages. However, the gap is expected to turn positive in the second half of 2027, alleviating supply tightness.

According to monitoring by Beating (Dongcha), China’s National Supercomputing Internet recently launched the Kimi K3 model API calling service. Enterprises and developers can quickly access large language model (LLM) capabilities without cumbersome environment configuration. The API is compatible with OpenAI and Anthropic interface specifications, enabling fast, low-cost deployment of diverse AI applications. Additionally, the Supercomputing Internet has rolled out the 100,000-Creation Plan, providing one-stop Model as a Service (MaaS) offerings.

Samsung Electronics is expanding its collaboration with Nvidia in the NAND flash memory sector. Industry sources revealed that Samsung has built V-NAND production capacity exceeding 100,000 wafers per month and is mass-producing its 10th-generation V10 products for supply to Nvidia. It is reported that Samsung has allocated approximately 60% of its V-NAND production capacity to V9 flash memory, a move aimed at meeting Nvidia’s demand for NAND for its CMX products set to launch in the second half of the year. In addition, Samsung has started trial production of 500-layer V11 flash memory; the trial production began earlier this year, and the company plans to double the related output in the second half of the year.

AMD will host its Advancing AI event in San Francisco from July 22 to 23, where more details about its MI500 series GPUs and scale-up Co-Packaged Optics (CPO) roadmap are set to be unveiled. In response to community queries, Serenity noted that if AMD explicitly commits to a CPO solution and discloses its optical engine supplier at the event, it will be a major positive for the entire CPO ecosystem—meaning NVIDIA is no longer the sole player driving the optical interconnect transition. Jefferies analyst Blayne Curtis currently expects AMD to partner with Astera Labs on UAL and Broadcom on ESUN, but the key watchpoint is whether AMD will officially shift to a CPO-based scale-up design and who will supply the optical engine. Serenity added that a clearer supply chain picture will only emerge after the event (held Wednesday and Thursday), so conclusions are premature for now. For Sivers, its supply chain ties to AMD’s CPO plans can only be inferred indirectly at present: first, GlobalFoundries (GF) is rumored to be involved in AMD’s MI500 CPO work, and Sivers is GF’s reference laser supplier; second, AMD has previously invested in Ayar Labs. If AMD confirms at the event that it will use Ayar Labs or GF’s SCALE as the optical engine for the MI500 CPO, it will be a massive boost for Sivers, which holds a core role as an upstream laser and reference laser supplier in both potential paths. The upcoming MI500 is expected to adopt a native UAL scale-up architecture, supporting 256 GPUs per rack and interconnected via optical links. Sivers has been steadily securing positions across multiple tech tracks this year, including CPO, pluggable optical modules, and silicon photonics. If AMD’s event confirms Sivers’ indirect entry into the supply chain, it will further validate the company’s full-scenario layout logic in the optical interconnect sector.